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Published in Proceedings of the 64th All-Russian Scientific Conference of MIPT, 2021
The paper is devoted to static verification of applications optimized by BOLT, which ensured the detection of errors on SPEC CPU 2017 when writing new optimizations.
Recommended citation: Lisitsyn S., Shurygin A. (2021). "Verification of static binary optimizing translation for RISC architecture" Proceedings of the 64th All-Russian Scientific Conference of MIPT. November 29 – December 03, 2021 Radio Engineering and Computer Technologies.
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Published in Proceedings of the 65th All-Russian Scientific Conference of MIPT in honor of the 115th anniversary of L.D. Landau, 2023
The paper is devoted to the development of an algorithm for generating a profile based on a binary execution trace under the RISC architecture. The output format of the Callgrind application was taken as a basis, so that it was possible to visualize the execution profile using KCachegrind.
Recommended citation: Shurygin A., Petushkov I. (2023). "Detailed profile generation and visualization for RISC architectures based on program execution traces." Proceedings of the 65th All-Russian Scientific Conference of MIPT in honor of the 115th anniversary of L.D. Landau, April 3–8, 2023. Radio engineering and computer technology..
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Published in Proceedings of MIPT, 2025
The paper solves the problem of analyzing the behavior of programs for RISC architectures based on binary execution traces. As part of the work, the profile generation algorithm was improved, and its subsequent visualization was supported using the KCachegrind application with an accuracy of up to linear sections of code. As a result of the work, accurate application execution profiles were obtained on the SPEC CPU 2017 performance benchmarks.
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Undergraduate elective course, Moscow Institute of Physics and Technology, Department of Radio Engineering and Computer Technology, 2024
The course is devoted to the topic of software modeling. The practical part of the course consists of implementing a functional model of the simulator for the RISC-V architecture. The course covers various technologies and optimizations for guest code execution.